forked from github/verilator
4a122fd0f2
* Add detailed location to XML output * Fixing build failures * less cryptic regulary expressions * correcting typo in test * Adding file letter to the location attribute, and cleaning up the regular expression in the tests. * Add remaining test expected output files for XML changes * spacing fix, adding documentation on changes
37 lines
1.1 KiB
Perl
Executable File
37 lines
1.1 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(vlt_all => 1);
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top_filename("t/t_trace_public.v");
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my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml";
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compile(
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make_top_shell => 0,
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make_main => 0,
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v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_public_sig.cpp $Self->{t_dir}/t_trace_public_sig.vlt"],
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);
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if ($Self->{vlt_all}) {
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file_grep("$out_filename", qr/\<var fl="e46" loc=".*?" name="GSR" dtype_id="1" vartype="logic" origName="GSR" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
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}
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execute(
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check_finished => 1,
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);
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vcd_identical("$Self->{obj_dir}/simx.vcd",
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"t/t_trace_public.out");
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# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;"
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file_grep("$Self->{obj_dir}/simx.vcd", qr/module glbl/i);
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ok(1);
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1;
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