forked from github/verilator
11 lines
232 B
Systemverilog
11 lines
232 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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`resetall // Ok
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module t;
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`resetall // Bad
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endmodule
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`resetall // Ok
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