forked from github/verilator
22088c907f
Adjust the maximum number width to 64K. Add --max-num-width option to adjust this setting. Closes #2082
9 lines
223 B
Systemverilog
9 lines
223 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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int a = -12'd1;
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int b = 65536'd1;
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int c = 1231232312312312'd1;
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