forked from github/verilator
18f8cd0529
* Add +verilator+noassert flag This allows to disable the assert check per simulation argument. * Add AssertOn check for assert Insert the check AssertOn to allow disabling of asserts. Asserts can be disabled by not using the `--assert` flag or by calling `AssertOn(false)`, or passing the "+verilator+noassert" runtime flag. Add tests for this behavior. Bad tests check that the assert still causes a stop. Non bad tests check that asserts are properly disabled and cause no stop of the simulation. Fixes #2162. Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org> * Correct file location Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org> * Add description for single test execution Without this description it is not obvious how to run a single test from the regression test suite. Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org>
19 lines
307 B
Systemverilog
19 lines
307 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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always @ (posedge clk) begin
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assert (0);
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$finish;
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end
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endmodule
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