forked from github/verilator
15 lines
451 B
Systemverilog
15 lines
451 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//
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// bug445
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`define WIDTH 12
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`define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS
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`define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS
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`define ADDR_BITS 0 +: `WIDTH-`SEL_NUM_BITS
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typedef logic [`SEL_NUM_BITS-1:0] d_t;
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