forked from github/verilator
14 lines
518 B
Systemverilog
14 lines
518 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// Test turning on and off a message on the same line; only middle reg shouldn't warn
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reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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