forked from github/verilator
35 lines
833 B
Systemverilog
35 lines
833 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`include "t_flag_f_tsub_inc.v"
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module t;
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initial begin
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`ifndef GOT_DEF1
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$write("%%Error: NO GOT_DEF1\n"); $stop;
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`endif
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`ifndef GOT_DEF2
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$write("%%Error: NO GOT_DEF2\n"); $stop;
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`endif
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`ifndef GOT_DEF3
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$write("%%Error: NO GOT_DEF3\n"); $stop;
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`endif
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`ifndef GOT_DEF4
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$write("%%Error: NO GOT_DEF4\n"); $stop;
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`endif
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`ifndef GOT_DEF5
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$write("%%Error: NO GOT_DEF5\n"); $stop;
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`endif
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`ifndef GOT_DEF6
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$write("%%Error: NO GOT_DEF6\n"); $stop;
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`endif
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`ifdef NON_DEF
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$write("%%Error: NON_DEF\n"); $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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