forked from github/verilator
25 lines
605 B
Systemverilog
25 lines
605 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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string a [string];
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string k;
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string v;
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v = a.num("badarg");
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v = a.size("badarg");
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v = a.exists(); // Bad
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v = a.exists(k, "bad2");
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v = a.first(); // Bad
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v = a.next(k, "bad2"); // Bad
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v = a.last(); // Bad
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v = a.prev(k, "bad2"); // Bad
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a.delete(k, "bad2");
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end
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endmodule
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