forked from github/verilator
185 lines
2.6 KiB
Plaintext
185 lines
2.6 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Fri Mar 14 20:31:17 2014
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 7 clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module v $end
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$var wire 1 7 clk $end
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$var wire 32 $ cyc [31:0] $end
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$var real 64 1 v_arr_real(0) $end
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$var real 64 3 v_arr_real(1) $end
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$var wire 2 ( v_arrp [2:1] $end
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$var wire 2 ) v_arrp_arrp [2:1] $end
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$var wire 2 * v_arrp_strp [1:0] $end
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$var wire 1 8 v_arru(1) $end
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$var wire 1 9 v_arru(2) $end
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$var wire 2 + v_arru_arrp(3) [2:1] $end
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$var wire 2 , v_arru_arrp(4) [2:1] $end
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$var wire 1 : v_arru_arru(3)(1) $end
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$var wire 1 ; v_arru_arru(3)(2) $end
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$var wire 1 < v_arru_arru(4)(1) $end
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$var wire 1 = v_arru_arru(4)(2) $end
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$var wire 2 - v_arru_strp(3) [1:0] $end
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$var wire 2 . v_arru_strp(4) [1:0] $end
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$var real 64 / v_real $end
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$var wire 2 % v_strp [1:0] $end
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$var wire 4 & v_strp_strp [3:0] $end
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$var wire 2 ' v_unip_strp [1:0] $end
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$scope module p2 $end
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$var wire 32 > PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 ? PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 5 b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 6 a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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