forked from github/verilator
591 lines
22 KiB
C++
591 lines
22 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Add temporaries, such as for inst nodes
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//
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// Code available from: http://www.veripool.org/verilator
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//
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//*************************************************************************
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//
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// Copyright 2003-2018 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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// V3Inst's Transformations:
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//
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// Each module:
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// Pins:
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// Create a wire assign to interconnect to submodule
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include <cstdio>
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#include <cstdarg>
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#include <unistd.h>
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#include <algorithm>
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#include "V3Global.h"
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#include "V3Inst.h"
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#include "V3Ast.h"
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#include "V3Changed.h"
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#include "V3Const.h"
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//######################################################################
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// Inst state, as a visitor of each AstNode
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class InstVisitor : public AstNVisitor {
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private:
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// NODE STATE
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// Cleared each Cell:
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// AstPin::user1p() -> bool. True if created assignment already
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AstUser1InUse m_inuser1;
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// STATE
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AstCell* m_cellp; // Current cell
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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//int m_debug; int debug() { return m_debug; }
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// VISITORS
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virtual void visit(AstCell* nodep) {
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UINFO(4," CELL "<<nodep<<endl);
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m_cellp = nodep;
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//VV***** We reset user1p() on each cell!!!
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AstNode::user1ClearTree();
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nodep->iterateChildren(*this);
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m_cellp = NULL;
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}
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virtual void visit(AstPin* nodep) {
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// PIN(p,expr) -> ASSIGNW(VARXREF(p),expr) (if sub's input)
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// or ASSIGNW(expr,VARXREF(p)) (if sub's output)
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UINFO(4," PIN "<<nodep<<endl);
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if (!nodep->exprp()) return; // No-connect
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if (debug()>=9) nodep->dumpTree(cout," Pin_oldb: ");
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if (nodep->modVarp()->isOutOnly() && nodep->exprp()->castConst())
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nodep->v3error("Output port is connected to a constant pin, electrical short");
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// Use user1p on the PIN to indicate we created an assign for this pin
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if (!nodep->user1SetOnce()) {
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// Simplify it
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V3Inst::pinReconnectSimple(nodep, m_cellp, false);
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// Make an ASSIGNW (expr, pin)
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AstNode* exprp = nodep->exprp()->cloneTree(false);
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if (exprp->width() != nodep->modVarp()->width())
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nodep->v3fatalSrc("Width mismatch, should have been handled in pinReconnectSimple");
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if (nodep->modVarp()->isInout()) {
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nodep->v3fatalSrc("Unsupported: Verilator is a 2-state simulator");
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} else if (nodep->modVarp()->isOutput()) {
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AstNode* rhsp = new AstVarXRef (exprp->fileline(), nodep->modVarp(), m_cellp->name(), false);
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AstAssignW* assp = new AstAssignW (exprp->fileline(), exprp, rhsp);
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m_cellp->addNextHere(assp);
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} else if (nodep->modVarp()->isInput()) {
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// Don't bother moving constants now,
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// we'll be pushing the const down to the cell soon enough.
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AstNode* assp = new AstAssignW
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(exprp->fileline(),
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new AstVarXRef(exprp->fileline(), nodep->modVarp(), m_cellp->name(), true),
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exprp);
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m_cellp->addNextHere(assp);
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if (debug()>=9) assp->dumpTree(cout," _new: ");
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} else if (nodep->modVarp()->isIfaceRef()
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|| (nodep->modVarp()->subDTypep()->castUnpackArrayDType()
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&& nodep->modVarp()->subDTypep()->castUnpackArrayDType()->subDTypep()->castIfaceRefDType())) {
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// Create an AstAssignVarScope for Vars to Cells so we can link with their scope later
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AstNode* lhsp = new AstVarXRef (exprp->fileline(), nodep->modVarp(), m_cellp->name(), false);
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AstVarRef* refp = exprp->castVarRef();
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AstVarXRef* xrefp = exprp->castVarXRef();
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if (!refp && !xrefp) exprp->v3fatalSrc("Interfaces: Pin is not connected to a VarRef or VarXRef");
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AstAssignVarScope* assp = new AstAssignVarScope(exprp->fileline(), lhsp, exprp);
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m_cellp->addNextHere(assp);
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} else {
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nodep->v3error("Assigned pin is neither input nor output");
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}
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}
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// We're done with the pin
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nodep->unlinkFrBack()->deleteTree(); VL_DANGLING(nodep);
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}
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virtual void visit(AstUdpTable* nodep) {
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if (!v3Global.opt.bboxUnsup()) {
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// If we support primitives, update V3Undriven to remove special case
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nodep->v3error("Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables.");
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}
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}
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// Save some time
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virtual void visit(AstNodeMath*) {}
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virtual void visit(AstNodeAssign*) {}
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virtual void visit(AstAlways*) {}
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//--------------------
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// Default: Just iterate
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virtual void visit(AstNode* nodep) {
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nodep->iterateChildren(*this);
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}
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public:
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// CONSTUCTORS
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explicit InstVisitor(AstNetlist* nodep) {
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m_cellp=NULL;
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//
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nodep->accept(*this);
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}
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virtual ~InstVisitor() {}
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};
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//######################################################################
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class InstDeModVarVisitor : public AstNVisitor {
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// Expand all module variables, and save names for later reference
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private:
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// STATE
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typedef map<string,AstVar*> VarNameMap;
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VarNameMap m_modVarNameMap; // Per module, name of cloned variables
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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// VISITORS
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virtual void visit(AstVar* nodep) {
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if (nodep->dtypep()->castIfaceRefDType()) {
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UINFO(8," dm-1-VAR "<<nodep<<endl);
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insert(nodep);
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}
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nodep->iterateChildren(*this);
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}
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// Save some time
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virtual void visit(AstNodeMath*) {}
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// Default: Just iterate
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virtual void visit(AstNode* nodep) {
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nodep->iterateChildren(*this);
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}
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public:
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// METHODS
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void insert(AstVar* nodep) {
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UINFO(8," dmINSERT "<<nodep<<endl);
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m_modVarNameMap.insert(make_pair(nodep->name(), nodep));
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}
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AstVar* find(const string& name) {
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VarNameMap::iterator it = m_modVarNameMap.find(name);
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if (it != m_modVarNameMap.end()) {
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return it->second;
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} else {
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return NULL;
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}
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}
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void dump() {
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for (VarNameMap::iterator it=m_modVarNameMap.begin(); it!=m_modVarNameMap.end(); ++it) {
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cout<<"-namemap: "<<it->first<<" -> "<<it->second<<endl;
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}
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}
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public:
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// CONSTUCTORS
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explicit InstDeModVarVisitor() {}
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void main(AstNodeModule* nodep) {
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UINFO(8," dmMODULE "<<nodep<<endl);
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m_modVarNameMap.clear();
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nodep->accept(*this);
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}
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virtual ~InstDeModVarVisitor() {}
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};
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//######################################################################
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class InstDeVisitor : public AstNVisitor {
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// Find all cells with arrays, and convert to non-arrayed
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private:
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// STATE
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AstRange* m_cellRangep; // Range for arrayed instantiations, NULL for normal instantiations
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int m_instSelNum; // Current instantiation count 0..N-1
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InstDeModVarVisitor m_deModVars; // State of variables for current cell module
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typedef map<string,AstVar*> VarNameMap;
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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// VISITORS
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virtual void visit(AstVar* nodep) {
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if (nodep->dtypep()->castUnpackArrayDType()
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&& nodep->dtypep()->castUnpackArrayDType()->subDTypep()->castIfaceRefDType()) {
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UINFO(8," dv-vec-VAR "<<nodep<<endl);
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AstUnpackArrayDType* arrdtype = nodep->dtypep()->castUnpackArrayDType();
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AstNode* prevp = NULL;
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for (int i = arrdtype->lsb(); i <= arrdtype->msb(); ++i) {
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string varNewName = nodep->name() + "__BRA__" + cvtToStr(i) + "__KET__";
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UINFO(8,"VAR name insert "<<varNewName<<" "<<nodep<<endl);
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if (!m_deModVars.find(varNewName)) {
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AstIfaceRefDType* ifaceRefp = arrdtype->subDTypep()->castIfaceRefDType()->cloneTree(false);
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arrdtype->addNextHere(ifaceRefp);
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ifaceRefp->cellp(NULL);
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AstVar* varNewp = nodep->cloneTree(false);
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varNewp->name(varNewName);
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varNewp->origName(varNewp->origName() + "__BRA__" + cvtToStr(i) + "__KET__");
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varNewp->dtypep(ifaceRefp);
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m_deModVars.insert(varNewp);
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if (!prevp) {
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prevp = varNewp;
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} else {
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prevp->addNextHere(varNewp);
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}
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}
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}
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if (prevp) nodep->addNextHere(prevp);
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if (prevp && debug()==9) { prevp->dumpTree(cout, "newintf: "); cout << endl; }
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstCell* nodep) {
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UINFO(4," CELL "<<nodep<<endl);
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// Find submodule vars
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if (!nodep->modp()) nodep->v3fatalSrc("Unlinked");
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m_deModVars.main(nodep->modp());
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//
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if (nodep->rangep()) {
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m_cellRangep = nodep->rangep();
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AstVar* ifaceVarp = nodep->nextp()->castVar();
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bool isIface = ifaceVarp
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&& ifaceVarp->dtypep()->castUnpackArrayDType()
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&& ifaceVarp->dtypep()->castUnpackArrayDType()->subDTypep()->castIfaceRefDType();
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// Make all of the required clones
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for (int i = 0; i < m_cellRangep->elementsConst(); i++) {
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m_instSelNum = m_cellRangep->littleEndian() ? (m_cellRangep->elementsConst() - 1 - i) : i;
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int instNum = m_cellRangep->lsbConst() + i;
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AstCell* newp = nodep->cloneTree(false);
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nodep->addNextHere(newp);
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// Remove ranging and fix name
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newp->rangep()->unlinkFrBack()->deleteTree();
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// Somewhat illogically, we need to rename the orignal name of the cell too.
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// as that is the name users expect for dotting
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// The spec says we add [x], but that won't work in C...
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newp->name(newp->name()+"__BRA__"+cvtToStr(instNum)+"__KET__");
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newp->origName(newp->origName()+"__BRA__"+cvtToStr(instNum)+"__KET__");
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UINFO(8," CELL loop "<<newp<<endl);
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// If this AstCell is actually an interface instantiation, also clone the IfaceRef
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// within the same parent module as the cell
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if (isIface) {
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AstUnpackArrayDType* arrdtype = ifaceVarp->dtypep()->castUnpackArrayDType();
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AstIfaceRefDType* origIfaceRefp = arrdtype->subDTypep()->castIfaceRefDType();
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origIfaceRefp->cellp(NULL);
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AstVar* varNewp = ifaceVarp->cloneTree(false);
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AstIfaceRefDType* ifaceRefp = arrdtype->subDTypep()->castIfaceRefDType()->cloneTree(false);
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arrdtype->addNextHere(ifaceRefp);
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ifaceRefp->cellp(newp);
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ifaceRefp->cellName(newp->name());
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varNewp->name(varNewp->name() + "__BRA__" + cvtToStr(instNum) + "__KET__");
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varNewp->origName(varNewp->origName() + "__BRA__" + cvtToStr(instNum) + "__KET__");
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varNewp->dtypep(ifaceRefp);
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newp->addNextHere(varNewp);
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if (debug()==9) { varNewp->dumpTree(cout, "newintf: "); cout << endl; }
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}
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// Fixup pins
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newp->pinsp()->iterateAndNext(*this);
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if (debug()==9) { newp->dumpTree(cout,"newcell: "); cout<<endl; }
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}
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// Done. Delete original
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m_cellRangep=NULL;
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if (isIface) {
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ifaceVarp->unlinkFrBack(); pushDeletep(ifaceVarp); VL_DANGLING(ifaceVarp);
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}
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nodep->unlinkFrBack(); pushDeletep(nodep); VL_DANGLING(nodep);
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} else {
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m_cellRangep = NULL;
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nodep->iterateChildren(*this);
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}
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}
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virtual void visit(AstPin* nodep) {
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// Any non-direct pins need reconnection with a part-select
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if (!nodep->exprp()) return; // No-connect
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if (m_cellRangep) {
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UINFO(4," PIN "<<nodep<<endl);
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int pinwidth = nodep->modVarp()->width();
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int expwidth = nodep->exprp()->width();
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pair<uint32_t,uint32_t> pinDim = nodep->modVarp()->dtypep()->dimensions(false);
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pair<uint32_t,uint32_t> expDim = nodep->exprp()->dtypep()->dimensions(false);
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UINFO(4," PINVAR "<<nodep->modVarp()<<endl);
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UINFO(4," EXP "<<nodep->exprp()<<endl);
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UINFO(4," pinwidth ew="<<expwidth<<" pw="<<pinwidth
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<<" ed="<<expDim.first<<","<<expDim.second
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<<" pd="<<pinDim.first<<","<<pinDim.second<<endl);
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if (expDim.first == pinDim.first && expDim.second == pinDim.second+1) {
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// Connection to array, where array dimensions match the instant dimension
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AstNode* exprp = nodep->exprp()->unlinkFrBack();
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exprp = new AstArraySel (exprp->fileline(), exprp,
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m_instSelNum);
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nodep->exprp(exprp);
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} else if (expwidth == pinwidth) {
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// NOP: Arrayed instants: widths match so connect to each instance
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} else if (expwidth == pinwidth*m_cellRangep->elementsConst()) {
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// Arrayed instants: one bit for each of the instants (each assign is 1 pinwidth wide)
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if (m_cellRangep->littleEndian()) {
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nodep->v3warn(LITENDIAN,"Little endian cell range connecting to vector: MSB < LSB of cell range: "
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<<m_cellRangep->lsbConst()<<":"<<m_cellRangep->msbConst());
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}
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AstNode* exprp = nodep->exprp()->unlinkFrBack();
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bool inputPin = nodep->modVarp()->isInput();
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if (!inputPin && !exprp->castVarRef()
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&& !exprp->castConcat() // V3Const will collapse the SEL with the one we're about to make
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&& !exprp->castSel()) { // V3Const will collapse the SEL with the one we're about to make
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nodep->v3error("Unsupported: Per-bit array instantiations with output connections to non-wires.");
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// Note spec allows more complicated matches such as slices and such
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}
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exprp = new AstSel (exprp->fileline(), exprp,
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pinwidth*m_instSelNum,
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pinwidth);
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nodep->exprp(exprp);
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} else {
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nodep->v3fatalSrc("Width mismatch; V3Width should have errored out.");
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}
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} else if (AstArraySel* arrselp = nodep->exprp()->castArraySel()) {
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if (AstUnpackArrayDType* arrp = arrselp->lhsp()->dtypep()->castUnpackArrayDType()) {
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if (!arrp->subDTypep()->castIfaceRefDType())
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return;
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V3Const::constifyParamsEdit(arrselp->rhsp());
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AstConst* constp = arrselp->rhsp()->castConst();
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if (!constp) {
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nodep->v3error("Unsupported: Non-constant index when passing interface to module");
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return;
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}
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string index = AstNode::encodeNumber(constp->toSInt());
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AstVarRef* varrefp = arrselp->lhsp()->castVarRef();
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AstVarXRef* newp = new AstVarXRef(nodep->fileline(), varrefp->name()+"__BRA__"+index+"__KET__", "", true);
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newp->dtypep(nodep->modVarp()->dtypep());
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newp->packagep(varrefp->packagep());
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arrselp->addNextHere(newp);
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arrselp->unlinkFrBack()->deleteTree();
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}
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} else {
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AstVar* pinVarp = nodep->modVarp();
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AstUnpackArrayDType* pinArrp = pinVarp->dtypep()->castUnpackArrayDType();
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if (!pinArrp || !pinArrp->subDTypep()->castIfaceRefDType())
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return;
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AstNode* prevp = NULL;
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AstNode* prevPinp = NULL;
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// Clone the var referenced by the pin, and clone each var referenced by the varref
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// Clone pin varp:
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for (int i = pinArrp->lsb(); i <= pinArrp->msb(); ++i) {
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string varNewName = pinVarp->name() + "__BRA__" + cvtToStr(i) + "__KET__";
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AstVar* varNewp = NULL;
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// Only clone the var once for all usages of a given child module
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if (!pinVarp->backp()) {
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varNewp = m_deModVars.find(varNewName);
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} else {
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AstIfaceRefDType* ifaceRefp = pinArrp->subDTypep()->castIfaceRefDType();
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ifaceRefp->cellp(NULL);
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varNewp = pinVarp->cloneTree(false);
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varNewp->name(varNewName);
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varNewp->origName(varNewp->origName() + "__BRA__" + cvtToStr(i) + "__KET__");
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varNewp->dtypep(ifaceRefp);
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m_deModVars.insert(varNewp);
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if (!prevp) {
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prevp = varNewp;
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} else {
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prevp->addNextHere(varNewp);
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}
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}
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if (!varNewp) {
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if (debug()>=9) m_deModVars.dump();
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nodep->v3fatalSrc("Module dearray failed for "<<AstNode::prettyName(varNewName));
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}
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// But clone the pin for each module instance
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// Now also clone the pin itself and update its varref
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AstPin* newp = nodep->cloneTree(false);
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newp->modVarp(varNewp);
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newp->name(newp->name() + "__BRA__" + cvtToStr(i) + "__KET__");
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// And replace exprp with a new varxref
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AstVarRef* varrefp = newp->exprp()->castVarRef();
|
||
string newname = varrefp->name() + "__BRA__" + cvtToStr(i) + "__KET__";
|
||
AstVarXRef* newVarXRefp = new AstVarXRef (nodep->fileline(), newname, "", true);
|
||
newVarXRefp->varp(newp->modVarp());
|
||
newVarXRefp->dtypep(newp->modVarp()->dtypep());
|
||
newp->exprp()->unlinkFrBack()->deleteTree();
|
||
newp->exprp(newVarXRefp);
|
||
if (!prevPinp) {
|
||
prevPinp = newp;
|
||
} else {
|
||
prevPinp->addNextHere(newp);
|
||
}
|
||
}
|
||
if (prevp) {
|
||
pinVarp->replaceWith(prevp);
|
||
pushDeletep(pinVarp);
|
||
} // else pinVarp already unlinked when another instance did this step
|
||
nodep->replaceWith(prevPinp);
|
||
pushDeletep(nodep);
|
||
}
|
||
}
|
||
|
||
// Save some time
|
||
virtual void visit(AstNodeMath*) {}
|
||
//--------------------
|
||
// Default: Just iterate
|
||
virtual void visit(AstNode* nodep) {
|
||
nodep->iterateChildren(*this);
|
||
}
|
||
public:
|
||
// CONSTUCTORS
|
||
explicit InstDeVisitor(AstNetlist* nodep) {
|
||
m_cellRangep=NULL;
|
||
m_instSelNum=0;
|
||
//
|
||
nodep->accept(*this);
|
||
}
|
||
virtual ~InstDeVisitor() {}
|
||
};
|
||
|
||
//######################################################################
|
||
// Inst static function
|
||
|
||
class InstStatic {
|
||
private:
|
||
static int debug() {
|
||
static int level = -1;
|
||
if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
|
||
return level;
|
||
}
|
||
InstStatic() {} // Static class
|
||
|
||
static AstNode* extendOrSel(FileLine* fl, AstNode* rhsp, AstNode* cmpWidthp) {
|
||
if (cmpWidthp->width() > rhsp->width()) {
|
||
rhsp = (rhsp->isSigned()
|
||
? static_cast<AstNode*>(new AstExtendS(fl, rhsp))
|
||
: static_cast<AstNode*>(new AstExtend (fl, rhsp)));
|
||
rhsp->dtypeFrom(cmpWidthp); // Need proper widthMin, which may differ from AstSel created above
|
||
} else if (cmpWidthp->width() < rhsp->width()) {
|
||
rhsp = new AstSel (fl, rhsp, 0, cmpWidthp->width());
|
||
rhsp->dtypeFrom(cmpWidthp); // Need proper widthMin, which may differ from AstSel created above
|
||
}
|
||
// else don't change dtype, as might be e.g. array of something
|
||
return rhsp;
|
||
}
|
||
|
||
public:
|
||
static AstAssignW* pinReconnectSimple(AstPin* pinp, AstCell* cellp,
|
||
bool forTristate, bool alwaysCvt) {
|
||
// If a pin connection is "simple" leave it as-is
|
||
// Else create a intermediate wire to perform the interconnect
|
||
// Return the new assignment, if one was made
|
||
// Note this module calles cloneTree() via new AstVar
|
||
|
||
AstVar* pinVarp = pinp->modVarp();
|
||
AstVarRef* connectRefp = pinp->exprp()->castVarRef();
|
||
AstVarXRef* connectXRefp = pinp->exprp()->castVarXRef();
|
||
AstBasicDType* pinBasicp = pinVarp->dtypep()->castBasicDType(); // Maybe NULL
|
||
AstBasicDType* connBasicp = NULL;
|
||
AstAssignW* assignp = NULL;
|
||
if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->castBasicDType();
|
||
//
|
||
if (!alwaysCvt
|
||
&& connectRefp
|
||
&& connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
|
||
&& !connectRefp->varp()->isSc()) { // Need the signal as a 'shell' to convert types
|
||
// Done. Same data type
|
||
} else if (!alwaysCvt
|
||
&& connectRefp
|
||
&& connectRefp->varp()->isIfaceRef()) {
|
||
// Done. Interface
|
||
} else if (!alwaysCvt
|
||
&& connectXRefp
|
||
&& connectXRefp->varp()
|
||
&& connectXRefp->varp()->isIfaceRef()) {
|
||
} else if (!alwaysCvt
|
||
&& connBasicp
|
||
&& pinBasicp
|
||
&& connBasicp->width() == pinBasicp->width()
|
||
&& connBasicp->lsb() == pinBasicp->lsb()
|
||
&& !connectRefp->varp()->isSc() // Need the signal as a 'shell' to convert types
|
||
&& connBasicp->width() == pinVarp->width()) {
|
||
// Done. One to one interconnect won't need a temporary variable.
|
||
} else if (!alwaysCvt && !forTristate && pinp->exprp()->castConst()) {
|
||
// Done. Constant.
|
||
} else {
|
||
// Make a new temp wire
|
||
//if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
|
||
AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
|
||
string newvarname = ((string)(pinVarp->isOutput() ? "__Vcellout" : "__Vcellinp")
|
||
+(forTristate?"t":"") // Prevent name conflict if both tri & non-tri add signals
|
||
+"__"+cellp->name()+"__"+pinp->name());
|
||
AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
|
||
// Important to add statement next to cell, in case there is a generate with same named cell
|
||
cellp->addNextHere(newvarp);
|
||
if (pinVarp->isInout()) {
|
||
pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be"
|
||
" direct one-to-one connection (without any expression)");
|
||
} else if (pinVarp->isOutput()) {
|
||
// See also V3Inst
|
||
AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, false);
|
||
UINFO(5,"pinRecon width "<<pinVarp->width()<<" >? "<<rhsp->width()<<" >? "<<pinexprp->width()<<endl);
|
||
rhsp = extendOrSel (pinp->fileline(), rhsp, pinVarp);
|
||
pinp->exprp(new AstVarRef (newvarp->fileline(), newvarp, true));
|
||
AstNode* rhsSelp = extendOrSel (pinp->fileline(), rhsp, pinexprp);
|
||
assignp = new AstAssignW (pinp->fileline(), pinexprp, rhsSelp);
|
||
} else {
|
||
// V3 width should have range/extended to make the widths correct
|
||
assignp = new AstAssignW (pinp->fileline(),
|
||
new AstVarRef(pinp->fileline(), newvarp, true),
|
||
pinexprp);
|
||
pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
|
||
}
|
||
if (assignp) cellp->addNextHere(assignp);
|
||
//if (debug()) { pinp->dumpTree(cout,"- out:"); }
|
||
//if (debug()) { assignp->dumpTree(cout,"- aout:"); }
|
||
}
|
||
return assignp;
|
||
}
|
||
};
|
||
|
||
//######################################################################
|
||
// Inst class functions
|
||
|
||
AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp,
|
||
bool forTristate, bool alwaysCvt) {
|
||
return InstStatic::pinReconnectSimple(pinp, cellp, forTristate, alwaysCvt);
|
||
}
|
||
|
||
//######################################################################
|
||
// Inst class visitor
|
||
|
||
void V3Inst::instAll(AstNetlist* nodep) {
|
||
UINFO(2,__FUNCTION__<<": "<<endl);
|
||
{
|
||
InstVisitor visitor (nodep);
|
||
} // Destruct before checking
|
||
V3Global::dumpCheckGlobalTree("inst", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3);
|
||
}
|
||
|
||
void V3Inst::dearrayAll(AstNetlist* nodep) {
|
||
UINFO(2,__FUNCTION__<<": "<<endl);
|
||
{
|
||
InstDeVisitor visitor (nodep);
|
||
} // Destruct before checking
|
||
V3Global::dumpCheckGlobalTree("dearray", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 6);
|
||
}
|