forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
45 lines
1013 B
Systemverilog
45 lines
1013 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg start = 0;
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reg [31:0] count;
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reg [31:0] runner = 0;
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always @ (posedge start) count = 0;
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always @ (posedge start) runner = 3;
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always @ (runner) begin
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if (runner > 0) begin
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$display("count=%d runner=%d",count, runner);
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count = count + 1;
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runner = runner - 1;;
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end
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end
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reg [7:0] cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 8'd1;
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case (cyc)
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8'd00: start <= 1'b0;
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8'd01: start <= 1'b1;
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8'd02: begin
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$display("Final count=%d", count);
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if (count!=32'h3) $stop;
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end
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default: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endcase
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end
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endmodule
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