forked from github/verilator
48 lines
1.0 KiB
Systemverilog
48 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This mode performs signed number computations in the case of a particular
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// interface definition.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Raynard Qiao.
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// SPDX-License-Identifier: CC0-1.0
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// issure 3294
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] in0;
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reg [7:0] in1;
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reg [15:0] out;
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initial begin
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in0 = 'h2;
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in1 = 'hff;
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end
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Test test(.in0, .in1, .out);
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out);
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`endif
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if (out !== 'hfffe) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Test(in0, in1, out);
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input [7:0] in0;
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input [7:0] in1;
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output [15:0] out;
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wire signed [7:0] in1;
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wire signed [7:0] in0;
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wire signed [15:0] out;
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assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication
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endmodule
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