forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
33 lines
668 B
Verilog
33 lines
668 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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initial begin
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if (add(3'd1) != 0) $stop; // Too few args
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if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args
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x; // Too few args
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if (hasout(3'd1) != 0) $stop; // outputs
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end
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function [2:0] add;
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input [2:0] from1;
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input [2:0] from2;
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begin
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add = from1 + from2;
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end
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endfunction
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task x;
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output y;
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begin end
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endtask
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function hasout;
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output [2:0] illegal_output;
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hasout = 0;
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endfunction
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endmodule
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