forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
28 lines
1.1 KiB
Perl
Executable File
28 lines
1.1 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id:$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2004 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# General Public License or the Perl Artistic License.
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top_filename("t/t_inst_overwide.v");
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compile (
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make_top_shell=>0,
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verilator_flags=> [qw(-sp)],
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verilator_make_gcc=>0,
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fails=>$Last_Self->{v3},
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expect=>
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'%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outy_w92 expects 92 bits but connection\'s VARREF generates 30 bits.
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%Warning-WIDTH: Use .* to disable this message.
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%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outz_w22 expects 22 bits but connection\'s VARREF generates 73 bits.
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%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inw_w31 expects 31 bits but connection\'s VARREF generates 1 bits.
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%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inx_w11 expects 11 bits but connection\'s VARREF generates 61 bits.
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%Error: Exiting due to.*',
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);
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ok(1);
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1;
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