forked from github/verilator
27 lines
493 B
Systemverilog
27 lines
493 B
Systemverilog
// DESCRIPTION: Verilator: Test of select from constant
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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o,
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// Inputs
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clk, i
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);
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input clk;
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input [3:0] i;
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output [3:0] o;
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logic [1:0][3:0] array;
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always_comb array[0] = i;
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always @ (posedge clk)
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array[1] <= array[0];
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assign o = array[1];
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endmodule
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