forked from github/verilator
10 lines
269 B
Systemverilog
10 lines
269 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (portwithoin);
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input portwithin;
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endmodule
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