forked from github/verilator
12 lines
324 B
Plaintext
12 lines
324 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2019 by Stefan Wallentowitz.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
`verilator_config
|
|
|
|
sc_bv -module "t" -var "ibv1_vlt"
|
|
sc_bv -module "*" -var "ibv16_vlt"
|
|
sc_bv -module "*" -var "obv*_vlt"
|