forked from github/verilator
23 lines
483 B
Systemverilog
23 lines
483 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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value
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);
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input [3:0] value;
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assign value = 4'h0;
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sub sub(.valueSub(value[3:0]));
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endmodule
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module sub (/*AUTOARG*/
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// Inputs
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valueSub
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);
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input [3:0] valueSub;
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assign valueSub = 4'h0;
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endmodule
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