forked from github/verilator
13 lines
455 B
Plaintext
13 lines
455 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Stefan Wallentowitz.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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isolate_assignments -module "file" -var "b"
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isolate_assignments -module "file" -task "set_b_d" -var "t_c*"
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isolate_assignments -module "file" -function "get_31_16" -var "t_crc"
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isolate_assignments -module "file" -function "get_31_16"
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