forked from github/verilator
47 lines
1.7 KiB
Raku
Executable File
47 lines
1.7 KiB
Raku
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett,
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# Embecosm.
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compile(
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# Taken from the original VCS command line.
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v_flags2 => ["t/t_sv_cpu_code/timescale.sv",
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"t/t_sv_cpu_code/program_h.sv",
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"t/t_sv_cpu_code/pads_h.sv",
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"t/t_sv_cpu_code/ports_h.sv",
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"t/t_sv_cpu_code/pinout_h.sv",
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"t/t_sv_cpu_code/genbus_if.sv",
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"t/t_sv_cpu_code/pads_if.sv",
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"t/t_sv_cpu_code/adrdec.sv",
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"t/t_sv_cpu_code/pad_gpio.sv",
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"t/t_sv_cpu_code/pad_vdd.sv",
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"t/t_sv_cpu_code/pad_gnd.sv",
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"t/t_sv_cpu_code/pads.sv",
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"t/t_sv_cpu_code/ports.sv",
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"t/t_sv_cpu_code/ac_dig.sv",
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"t/t_sv_cpu_code/ac_ana.sv",
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"t/t_sv_cpu_code/ac.sv",
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"t/t_sv_cpu_code/cpu.sv",
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"t/t_sv_cpu_code/chip.sv"],
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vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"],
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verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t"],
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iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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