forked from github/verilator
64 lines
1.6 KiB
Systemverilog
64 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// packed structures
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struct packed {
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logic e0;
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logic [1:0] e1;
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logic [3:0] e2;
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logic [7:0] e3;
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} struct_bg; // big endian structure
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/* verilator lint_off LITENDIAN */
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struct packed {
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logic e0;
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logic [0:1] e1;
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logic [0:3] e2;
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logic [0:7] e3;
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} struct_lt; // little endian structure
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/* verilator lint_on LITENDIAN */
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integer cnt = 0;
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// event counter
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always @ (posedge clk)
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begin
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cnt <= cnt + 1;
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end
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// finish report
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always @ (posedge clk)
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if (cnt==2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @ (posedge clk)
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if (cnt==1) begin
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// big endian
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if ($bits (struct_bg ) != 15) $stop;
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if ($bits (struct_bg.e0) != 1) $stop;
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if ($bits (struct_bg.e1) != 2) $stop;
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if ($bits (struct_bg.e2) != 4) $stop;
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if ($bits (struct_bg.e3) != 8) $stop;
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if ($increment (struct_bg, 1) != 1) $stop;
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// little endian
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if ($bits (struct_lt ) != 15) $stop;
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if ($bits (struct_lt.e0) != 1) $stop;
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if ($bits (struct_lt.e1) != 2) $stop;
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if ($bits (struct_lt.e2) != 4) $stop;
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if ($bits (struct_lt.e3) != 8) $stop;
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if ($increment (struct_lt, 1) != 1) $stop; // Structure itself always big numbered
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end
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endmodule
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