forked from github/verilator
47 lines
1.4 KiB
Systemverilog
47 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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// See also t_math_width
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// This shows the uglyness in width warnings across param modules
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// TODO: Would be nice to also show relevant parameter settings
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p #(.WIDTH(4)) p4 (.in(4'd0));
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p #(.WIDTH(5)) p5 (.in(5'd0));
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//====
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localparam [3:0] XS = 'hx; // User presumably intended to use 'x
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//====
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wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax
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wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is
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//====
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localparam WIDTH = 6;
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wire one_bit;
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wire [2:0] shifter = 1;
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wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
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//====
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// We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
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wire one = 1;
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wire [2:0] cnt = (one + one + one + one);
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// Not harmless > or >= compared with something wider (as different results if "a" wider)
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localparam [40:0] THREE = 3;
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int a;
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initial for (a = 0; a > THREE; ++a) $display(a);
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initial for (a = 0; a >= THREE; ++a) $display(a);
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endmodule
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module p
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#(parameter WIDTH=64)
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(input [WIDTH-1:0] in);
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wire [4:0] out = in;
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endmodule
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