forked from github/verilator
11 lines
256 B
Systemverilog
11 lines
256 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2010 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
`include "/dev/null"
|
|
|
|
module t;
|
|
endmodule
|