forked from github/verilator
29 lines
547 B
Systemverilog
29 lines
547 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (a,z);
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input a;
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output z;
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sub sub ();
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assign imp_warn = 1'b1;
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// verilator lint_off IMPLICIT
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assign imp_ok = 1'b1;
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`default_nettype none
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assign imp_err = 1'b1;
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`default_nettype wire
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assign imp_ok2 = 1'b1;
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endmodule
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`default_nettype none
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`resetall
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module sub;
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assign imp_ok3 = 1'b1;
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endmodule
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