forked from github/verilator
14 lines
382 B
Systemverilog
14 lines
382 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test of the +verilog2001ext+ and +verilog2005ext+ flags.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off SYMRSVDWORD
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module t(input do);
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t_langext_order_sub sub (.do(do));
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endmodule
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