forked from github/verilator
47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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function integer get_baz(input integer bar);
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get_baz = bar;
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$fatal(2, "boom");
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endfunction
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module foo #(parameter BAR = 0);
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localparam integer BAZ = get_baz(BAR);
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endmodule
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module foo2 #(parameter QUX = 0);
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genvar x;
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generate
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for (x = 0; x < 2; x++) begin: foo2_loop
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foo #(.BAR (QUX + x)) foo_in_foo2_inst();
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end
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endgenerate
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endmodule
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module t;
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genvar i, j;
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generate
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for (i = 0; i < 2; i++) begin: genloop
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foo #(.BAR (i)) foo_inst();
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end
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for (i = 2; i < 4; i++) begin: gen_l1
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for (j = 0; j < 2; j++) begin: gen_l2
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foo #(.BAR (i + j*2)) foo_inst2();
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end
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end
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if (1 == 1) begin: cond_true
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foo #(.BAR (6)) foo_inst3();
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end
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if (1 == 1) begin // unnamed
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foo #(.BAR (7)) foo_inst4();
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end
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for (i = 8; i < 12; i = i + 2) begin: nested_loop
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foo2 #(.QUX (i)) foo2_inst();
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end
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endgenerate
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endmodule
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