forked from github/verilator
29 lines
603 B
Systemverilog
29 lines
603 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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function automatic integer min(input integer a, input integer b);
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return (a < b) ? a : b;
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endfunction
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module t
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#(parameter A=16, parameter B=8)
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(/*AUTOARG*/
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// Outputs
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c,
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// Inputs
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a, b
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);
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input [A-1:0] a;
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input [B-1:0] b;
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output logic [min(A,B)-1:0] c;
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always_comb
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for (int i = 0; i < min(A,B); i++)
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assign c[i] = a[i] | b[i];
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endmodule
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