forked from github/verilator
176 lines
3.4 KiB
Plaintext
176 lines
3.4 KiB
Plaintext
// verilator_coverage annotation
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg toggle; initial toggle=0;
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integer cyc; initial cyc=1;
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wire [7:0] cyc_copy = cyc[7:0];
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alpha a1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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alpha a2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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beta b1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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beta b2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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tsk t1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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off o1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle));
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always @ (posedge clk) begin
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000010 if (cyc!=0) begin
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cyc <= cyc + 1;
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toggle <= '0;
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%000001 if (cyc==3) begin
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toggle <= '1;
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end
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%000001 else if (cyc==5) begin
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`ifdef VERILATOR
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$c("call_task();");
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`else
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call_task();
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`endif
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end
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%000001 else if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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task call_task;
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/* verilator public */
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t1.center_task(1'b1);
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endtask
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endmodule
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module alpha (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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always @ (posedge clk) begin
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%000002 if (toggle) begin
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// CHECK_COVER(-1,"top.t.a*",2)
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// t.a1 and t.a2 collapse to a count of 2
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end
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if (toggle) begin
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// CHECK_COVER_MISSING(-1)
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// This doesn't even get added
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`ifdef ATTRIBUTE
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// verilator coverage_block_off
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`endif
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$write("");
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end
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end
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endmodule
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module beta (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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/* verilator public_module */
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always @ (posedge clk) begin
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%000000 if (0) begin
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// CHECK_COVER(-1,"top.t.b*",0)
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// Make sure that we don't optimize away zero buckets
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end
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%000002 if (toggle) begin
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// CHECK_COVER(-1,"top.t.b*",2)
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// t.b1 and t.b2 collapse to a count of 2
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end
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if (toggle) begin : block
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// CHECK_COVER_MISSING(-1)
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// This doesn't
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`ifdef ATTRIBUTE
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// verilator coverage_block_off
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`endif
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$write("");
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end
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end
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endmodule
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module tsk (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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/* verilator public_module */
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always @ (posedge clk) begin
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center_task(1'b0);
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end
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task center_task;
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input external;
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begin
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%000001 if (toggle) begin
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// CHECK_COVER(-1,"top.t.t1",1)
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end
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%000001 if (external) begin
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// CHECK_COVER(-1,"top.t.t1",1)
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$write("[%0t] Got external pulse\n", $time);
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end
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end
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endtask
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endmodule
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module off (/*AUTOARG*/
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// Inputs
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clk, toggle
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);
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input clk;
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input toggle;
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// verilator coverage_off
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always @ (posedge clk) begin
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if (toggle) begin
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// CHECK_COVER_MISSING(-1)
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// because under coverage_module_off
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end
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end
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// verilator coverage_on
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always @ (posedge clk) begin
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%000001 if (toggle) begin
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// CHECK_COVER(-1,"top.t.o1",1)
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// because under coverage_module_off
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end
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end
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endmodule
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