forked from github/verilator
41 lines
998 B
Systemverilog
41 lines
998 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Pkg;
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typedef enum { ENUMP_VAL = 33 } enump_t;
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endpackage
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module t (/*AUTOARG*/);
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class Cls;
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int imembera;
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int imemberb;
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typedef enum { ENUM_VAL = 22 } enum_t;
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endclass : Cls
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Cls c;
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Cls d;
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initial begin
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// Alternate between two versions to make sure we don't
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// constant propagate between them.
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c = new;
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d = new;
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c.imembera = 10;
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d.imembera = 11;
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c.imemberb = 20;
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d.imemberb = 21;
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if (c.imembera != 10) $stop;
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if (d.imembera != 11) $stop;
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if (c.imemberb != 20) $stop;
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if (d.imemberb != 21) $stop;
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if (Pkg::ENUMP_VAL != 33) $stop;
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if (Cls::ENUM_VAL != 22) $stop;
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if (c.ENUM_VAL != 22) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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