forked from github/verilator
4 lines
159 B
Plaintext
4 lines
159 B
Plaintext
[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found
|
|
%Error: t/t_assert_synth.v:31: Verilog $stop
|
|
Aborting...
|