forked from github/verilator
31 lines
654 B
Systemverilog
31 lines
654 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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nnext,
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// Inputs
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inibble, onibble
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);
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input [3:0] inibble;
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input [106:0] onibble;
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output reg [3:0] nnext [0:7];
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// verilator lint_off WIDTH
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wire [2:0] selline = (onibble >>> 102) & 7;
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// verilator lint_on WIDTH
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always_comb begin
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for (integer i=0; i<8; i=i+1) begin
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nnext[i] = '0;
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end
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nnext[selline] = inibble;
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end
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endmodule
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