forked from github/verilator
7 lines
246 B
Systemverilog
7 lines
246 B
Systemverilog
// DESCRIPTION: Verilog::Preproc: Example source code
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2000-2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define T_PREPROC_INC4
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