verilator/test_regress/t/t_trace_public.out

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$version Generated by VerilatedVcd $end
$date Tue Aug 10 15:49:51 2021 $end
$timescale 1ps $end
$scope module top $end
$var wire 1 5 CLK $end
$var wire 1 6 RESET $end
$scope module t $end
$var wire 1 5 CLK $end
$var wire 1 # RESET $end
$var wire 32 & val [31:0] $end
$var wire 2 $ vec[3] [2:1] $end
$var wire 2 % vec[4] [2:1] $end
$scope module glbl $end
$var wire 1 7 GSR $end
$upscope $end
$scope module little $end
$var wire 1 5 clk $end
$var wire 128 1 i128 [63:190] $end
$var wire 49 / i48 [1:49] $end
$var wire 8 . i8 [0:7] $end
$upscope $end
$scope module neg $end
$var wire 1 5 clk $end
$var wire 128 * i128 [63:-64] $end
$var wire 48 ( i48 [-1:-48] $end
$var wire 8 ' i8 [0:-7] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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