forked from github/verilator
120 lines
3.4 KiB
Systemverilog
120 lines
3.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer p_i; // signal type IData
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reg [15:0] p_s; // signal type SData
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reg [7:0] p_c; // signal type CData
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real p_r; // signal type double
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reg [7*8:1] p_str;
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string sv_str;
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reg [7*8:1] p_in;
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string sv_in;
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initial begin
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if ($test$plusargs("PLUS")!==1) $stop;
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if ($test$plusargs("PLUSNOT")!==0) $stop;
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if ($test$plusargs("PL")!==1) $stop;
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//if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer
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if ($test$plusargs("NOTTHERE")!==0) $stop;
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p_i = 10;
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if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop;
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if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop;
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if (p_i !== 10) $stop;
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p_i = 0;
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if ($value$plusargs("INT=%d", p_i) !== 1) $stop;
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if (p_i !== 32'd1234) $stop;
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p_i = 0;
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if ($value$plusargs("INT=%0d", p_i) !== 1) $stop;
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if (p_i !== 32'd1234) $stop;
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p_i = 0;
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if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also
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if (p_i !== 32'h1234) $stop;
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p_i = 0;
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// Check octal and WIDTH
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if (!$value$plusargs("INT=%o", p_i)) $stop;
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if (p_i !== 32'o1234) $stop;
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// Check handling of 'SData' type signals (Issue #1592)
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p_s = 0;
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if (!$value$plusargs("INT=%d", p_s)) $stop;
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if (p_s !== 16'd1234) $stop;
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// Check handling of 'CData' type signals (Issue #1592)
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p_c = 0;
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if (!$value$plusargs("INT=%d", p_c)) $stop;
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if (p_c !== 8'd210) $stop;
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// Check handling of 'double' type signals (Issue #1619)
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p_r = 0;
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if (!$value$plusargs("REAL=%e", p_r)) $stop;
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$display("r='%e'", p_r);
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if (p_r !== 1.2345) $stop;
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p_r = 0;
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if (!$value$plusargs("REAL=%f", p_r)) $stop;
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$display("r='%f'", p_r);
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if (p_r !== 1.2345) $stop;
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p_r = 0;
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if (!$value$plusargs("REAL=%g", p_r)) $stop;
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$display("r='%g'", p_r);
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if (p_r !== 1.2345) $stop;
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p_str = "none";
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if ($value$plusargs("IN%s", p_str)!==1) $stop;
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$display("str='%s'",p_str);
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if (p_str !== "T=1234") $stop;
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sv_str = "none";
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if ($value$plusargs("IN%s", sv_str)!==1) $stop;
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$display("str='%s'",sv_str);
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if (sv_str != "T=1234") $stop;
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sv_str = "none";
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$value$plusargs("IN%s", sv_str);
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$display("str='%s'",sv_str);
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if (sv_str != "T=1234") $stop;
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p_in = "IN%s";
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`ifdef VERILATOR
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p_in = $c(p_in); // Prevent constant propagation
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`endif
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sv_str = "none";
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if ($value$plusargs(p_in, sv_str)!==1) $stop;
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$display("str='%s'",sv_str);
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if (sv_str != "T=1234") $stop;
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sv_str = "none";
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if ($value$plusargs("IP%%P%b", p_i)!==1) $stop;
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$display("str='%s'",sv_str);
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if (p_i != 'b101) $stop;
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sv_in = "INT=%d";
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`ifdef VERILATOR
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if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation
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`endif
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p_i = 0;
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if ($value$plusargs(sv_in, p_i)!==1) $stop;
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$display("i='%d'",p_i);
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if (p_i !== 32'd1234) $stop;
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// bug3131 - really "if" side effect test
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p_i = 0;
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if ($value$plusargs("INT=%d", p_i)) ;
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if (p_i !== 32'd1234) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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