forked from github/verilator
31 lines
475 B
Systemverilog
31 lines
475 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define FOO
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`define BAR(aa,bb) aa bb
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`FOO
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`BAR(aa,bb)
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`ifdef FOO
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`else
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`endif
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`ifndef FOO
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`elsif FOO
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`endif
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`define STRINGIFY(x) `"x`"
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`define CONCAT(a, b) a``b
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`STRINGIFY(x)
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`CONCAT(x,y)
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`undef FOO
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`undefineall
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`ifdef NEVER
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`error "should not get"
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`endif
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