forked from github/verilator
51 lines
1.3 KiB
Systemverilog
51 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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logic [7:0] subnet;
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sub1 sub1(.*);
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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`checkh(subnet, 8'h11);
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force sub1.subnet = 8'h01; // sub1.subnet same as subnet
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end
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else if (cyc == 11) begin
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`checkh(subnet, 8'h01);
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force subnet = 8'h10; // sub1.subnet same as subnet
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end
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else if (cyc == 12) begin
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`checkh(subnet, 8'h10);
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release subnet; // sub1.subnet same as subnet
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end
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else if (cyc == 13) begin
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`checkh(subnet, 8'h11);
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end
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//
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub1(output logic [7:0] subnet);
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assign subnet = 8'h11;
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endmodule
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