forked from github/verilator
67bb2c640e
This is a pre-PR to #3363, which will introduce more clock gen tests. Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
42 lines
925 B
Systemverilog
42 lines
925 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module clkgen(output bit clk);
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initial begin
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#(8.0:5:3) clk = 1; // Middle is default
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forever begin
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#5 clk = ~clk;
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end
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end
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endmodule
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module t(/*AUTOARG*/);
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wire logic clk;
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clkgen clkgen (.clk);
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int cyc;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$display("[%0t] cyc=%0d", $time, cyc);
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`endif
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if (cyc == 0) begin
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if ($time != 5) $stop;
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end
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else if (cyc == 1) begin
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if ($time != 15) $stop;
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end
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else if (cyc == 2) begin
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if ($time != 25) $stop;
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end
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else if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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