forked from github/verilator
8 lines
509 B
Plaintext
8 lines
509 B
Plaintext
%Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits.
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: ... In instance t
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21 | reg width_warn3_var_line20 = 2'b11;
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| ^~~~~
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... For warning description see https://verilator.org/warn/WIDTH?v=latest
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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%Error: Exiting due to
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