forked from github/verilator
40 lines
1.0 KiB
Systemverilog
40 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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localparam logic [9:0] V2 = (1 << 2);
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localparam logic [9:0] V1 = (1 << 1);
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localparam logic [9:0] V0 = (1 << 0);
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typedef enum logic [9:0] {
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ZERO = '0,
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VAL0 = V0,
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VAL1 = V1,
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VAL01 = V0 | V1
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} enum_t;
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localparam enum_t PARAMVAL1 = VAL1;
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localparam enum_t PARAMVAL1CONST = enum_t'(2);
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typedef enum {I_ZERO, I_ONE, I_TWO} inte_t;
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localparam inte_t I_PARAM = inte_t'(1);
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initial begin
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enum_t e;
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e = VAL01;
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if (e != VAL01) $stop;
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if (PARAMVAL1 != VAL1) $stop;
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if (PARAMVAL1CONST != VAL1) $stop;
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if (I_PARAM != I_ONE) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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