forked from github/verilator
15 lines
382 B
Systemverilog
15 lines
382 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Michael Lefebvre.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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localparam int unsigned A3 [2:0] = '{4,5,6};
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// slicesel out of range should fail
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localparam int unsigned B32_T [1:0] = A3[3:1];
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endmodule
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