forked from github/verilator
75 lines
1.8 KiB
Systemverilog
75 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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always @(negedge clk) begin // negedge so there is nothing after $finish
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cyc <= cyc + 1;
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if (cyc == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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logic genclk = 0, a = 0, b = 1, c = 0, x = 0, y, z = 0;
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always @(edge clk) genclk = clk;
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always @(posedge genclk) $display("%0t | posedge", $time);
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// Clocking block
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clocking cb @(posedge genclk);
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input #0 a, y;
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input #1step b;
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output #0 x;
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`ifdef VERILATOR_TIMING
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output #2 z;
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`endif
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endclocking
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// Print after Observed
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always @(posedge genclk) a = ~a;
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always @cb $display("%0t | cb.a=%b", $time, cb.a);
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always @cb $display("%0t | cb.b=%b", $time, cb.b);
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always @cb.y $display("%0t | cb.y=%b", $time, cb.y);
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// Retrigger everything after Observed
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always @cb.a b = x;
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always @b begin
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$display("%0t | b=%b", $time, b);
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if (b == 0) genclk = ~genclk;
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end
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// Do an NBA
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always @(posedge genclk) c <= ~c;
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always @c begin
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$display("%0t | c<=%b", $time, c);
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end
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// Print after Re-NBA
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always @(posedge genclk) cb.x <= ~x;
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always @x $display("%0t | x<=%b", $time, x);
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// Retrigger everything after Re-NBA
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always @x y = x;
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always @y begin
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$display("%0t | y=%b", $time, y);
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if (y == 1) genclk = ~genclk;
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end
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`ifdef VERILATOR_TIMING
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// Print after delay and Re-NBA
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always @(posedge genclk) cb.z <= ~z;
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always @z $display("%0t | z<=%b", $time, z);
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`endif
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// Print in Postponed
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always @(posedge genclk) $strobe("%0t | %b %b %b %b %b %b", $time, a, b, c, x, y, z);
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endmodule;
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