forked from github/verilator
44 lines
1012 B
Systemverilog
44 lines
1012 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class paramed_class_t;
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typedef class arg_class_t;
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typedef paramed_class_t#(logic[3:0], 1) paramed_class_logic4_t;
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virtual class vclass #(type CTYPE_t = arg_class_t, int I = 0);
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pure virtual function void funcname(paramed_class_t #(CTYPE_t) v);
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endclass
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class paramed_class_t #(type TYPE, int I = 0);
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TYPE memb;
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endclass
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class arg_class_t;
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int ifield;
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endclass
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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vclass vir;
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paramed_class_t#(arg_class_t) argu;
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initial begin
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argu = new;
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argu.memb = new;
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argu.memb.ifield = 1234;
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// vir.funcname(argu);
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if (argu.memb.ifield != 1234) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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