forked from github/verilator
0722f47539
V3MergeCond merges consecutive conditional `_ = cond ? _ : _` and `if (cond) ...` statements. This patch adds an analysis and ordering phase that moves statements with identical conditions closer to each other, in order to enable more merging opportunities. This in turn eliminates a lot of repeated conditionals which reduced dynamic branch count and branch misprediction rate. Observed 6.5% improvement on multi-threaded large designs, at the cost of less than 2% increase in Verilation speed.
33 lines
1009 B
Perl
Executable File
33 lines
1009 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt_all => 1);
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compile(
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verilator_flags2 => ["-unroll-count 64", "--stats"],
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);
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execute(
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check_finished => 1,
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);
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if ($Self->{vlt}) {
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# Note, with vltmt this might be split differently, so only checking vlt
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file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i,
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9);
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file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i,
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580);
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file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i,
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128);
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}
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ok(1);
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1;
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