forked from github/verilator
24 lines
456 B
Systemverilog
24 lines
456 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1s/1s
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module t;
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sub sub ();
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initial begin
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$printtimescale;
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sub.pts();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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task pts;
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$printtimescale;
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endtask
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endmodule
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