forked from github/verilator
d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
51 lines
1.7 KiB
Systemverilog
51 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale `time_scale_units / `time_scale_prec
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import "DPI-C" function void dpii_check();
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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// verilator lint_off REALCVT
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time digits = 5432109876.543210ns; // Will round to time units
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realtime rdigits = 5432109876.543210ns; // Will round to time precision
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// verilator lint_on REALCVT
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("- [%0t] tick\n", $time);
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`endif
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if ($time >= 60) begin
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$write(":: In %m\n");
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$printtimescale;
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$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
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$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
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$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
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$timeformat(-9, 6, "ns", 16);
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$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
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$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
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$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
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$write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n",
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$time, $stime, $stime, $stime);
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// verilator lint_off REALCVT
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$write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n",
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$time, $realtime, $realtime, $realtime);
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// verilator lint_on REALCVT
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dpii_check();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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