forked from github/verilator
62 lines
1.4 KiB
Systemverilog
62 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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// Also check that SystemC is ordering properly
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// verilator lint_on IMPERFECTSCH
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module t (/*AUTOARG*/
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// Outputs
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o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16,
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// Inputs
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clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16
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);
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input clk;
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input i1;
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input [7:0] i8;
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input [15:0] i16;
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input [31:0] i32;
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input [63:0] i64;
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input [64:0] i65;
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input [127:0] i128;
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input [512:0] i513;
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input i1a2 [1:0];
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input [93:0] i94a3 [2:0];
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output logic o1;
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output logic [7:0] o8;
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output logic [15:0] o16;
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output logic [31:0] o32;
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output logic [63:0] o64;
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output logic [64:0] o65;
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output logic [127:0] o128;
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output logic [512:0] o513;
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output logic o1a2 [1:0];
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output logic [93:0] o94a3 [2:0];
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input [0:0] ibv1 /*verilator sc_bv*/;
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input [15:0] ibv16 /*verilator sc_bv*/;
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output logic [0:0] obv1 /*verilator sc_bv*/;
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output logic [15:0] obv16 /*verilator sc_bv*/;
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always @ (posedge clk) begin
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o1 <= i1;
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o8 <= i8;
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o16 <= i16;
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o32 <= i32;
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o64 <= i64;
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o65 <= i65;
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o128 <= i128;
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o513 <= i513;
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obv1 <= ibv1;
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obv16 <= ibv16;
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o1a2 <= i1a2;
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o94a3 <= i94a3;
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end
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endmodule
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