forked from github/verilator
1e938d0e90
Fix preprocessor preservation of newlines across macro substitutions. Fix preprocessor stringification of nested macros. Fix preprocessor whitespace on define arguments
6 lines
192 B
Systemverilog
6 lines
192 B
Systemverilog
// DESCRIPTION: Verilog::Preproc: Example source code
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2000-2010 by Wilson Snyder.
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`define T_PREPROC_INC4
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