forked from github/verilator
21 lines
486 B
Systemverilog
21 lines
486 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(/*AUTOARG*/);
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int sig;
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initial begin
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sig = 10;
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$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
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$dumpvars();
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#20;
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sig = 20;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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