forked from github/verilator
19 lines
468 B
Systemverilog
19 lines
468 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls #(type REQ=int);
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extern virtual function void extfunc();
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endclass
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function void Cls::extfunc();
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REQ t; // Declared in class when externed, so must be found there
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endfunction
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module f;
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function void normal();
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endfunction
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endmodule
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