forked from github/verilator
16 lines
330 B
Systemverilog
16 lines
330 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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z
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);
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reg [3:0] r = 4'b1010;
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output [2:1] z = r[2 :+ 1];
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endmodule
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